1. Field of the Invention
The present invention relates to a lock detection circuit and a lock detecting method, and more particularly, to a lock detection circuit capable of detecting a lock state of a phase locked loop (PLL) circuit and a lock detecting method.
2. Discussion of Related Art
In transmitting and receiving a digital signal using a digital clock, in order to clearly identify whether a received signal is 0 or 1, it is necessary to accurately discern a location where each clock starts and stops. However, transmitting a signal in a wired or wireless configuration causes the signal to be delayed according to a signal path, and its phase to be changed as well. Therefore, it may be unclear for a receiving part to know which parts correspond to a start point and a stop point to determine 0 and 1.
Under these circumstances, a circuit that synchronizes a start point of a clock with its stop point is required, and a phase locked loop (PLL) circuit functions to synchronize a start (0 degree) with a stop (360 degrees) of a period.
The PLL circuit compares a phase of a reference signal with that of a feedback signal from a voltage controlled oscillator (VCO) to synchronize the phase. It is used in various applications such as a communication system, etc. Thanks to recent developments in semiconductor technology, the PLL circuit can be implemented as semiconductor integrated circuit.
FIG. 1 is a block diagram of a general PLL circuit.
Referring to FIG. 1, a PLL circuit 100 includes a first frequency divider 110 dividing a frequency of a reference signal FREF, a second frequency divider 120 dividing a frequency of a feedback signal FVCO, a phase frequency detector 130 comparing a phase of a frequency-divided reference signal FREF′ with that of a frequency-divided feedback signal FVCO′ to output an up signal UP or a down signal DN depending on a phase difference, a lock detection circuit 140 detecting a lock state according to the up signal UP or the down signal DN output from the phase frequency detector 130 to output a low or high lock detection signal LKD, a charge pump 150 pumping charge according to the up signal UP or the down signal DN output from the phase frequency detector 130, a loop filter 160 filtering a high frequency component from the signal output from the charge pump 150, and a VCO 170 varying a frequency of the output signal FVCO according to a control voltage output from the loop filter 160.
When a phase of the frequency-divided reference signal FREF′ is faster than that of the frequency-divided feedback signal FVCO′, the PLL circuit 100 raises an oscillation frequency so that a phase of the feedback signal FVCO becomes faster. Also, when a phase of the frequency-divided reference signal FREF′ is slower than that of the frequency-divided feedback signal FVCO′, the PLL circuit 100 lowers an oscillation frequency so that the phase of the feedback signal FVCO becomes delayed.
When the phase of the frequency-divided reference signal FREF′ and that of the frequency-divided feedback signal FVCO′ are locked by the synchronization, i.e., a high lock detection signal LKD is output from the lock detection circuit 140, an output of the VCO 170 may be used for various application circuits.
Therefore, the lock detection circuit 140 is able to accurately detect the lock state of the PLL circuit, and for this purpose, it is necessary for the up signal UP and the down signal DN, which are output from the phase frequency detector 130, to have an accurate state value.
The state value of the up signal UP and the down signal DN, which are output from the phase frequency detector 130, will be described below in detail.
FIG. 2A is a circuit diagram of a three-state phase frequency detector that is generally used in a PLL circuit, FIG. 2B illustrates a state machine of the phase frequency detector illustrated in FIG. 2A, and FIG. 2C is a timing diagram of the phase frequency detector illustrated in FIG. 2A.
Referring to FIG. 2A, the three-state phase frequency detector includes two D flip-flops and one AND gate, and in the detector, a phase difference between a frequency-divided reference signal FREF′ and a frequency-divided feedback signal FVCO′ is detected at rising edges of the two signals to output an up signal UP and a down signal DN. Here, as illustrated in FIG. 2B, when a phase of the frequency-divided reference signal FREF′ is faster than that of the frequency-divided feedback signal FVCO′, the state value moves to “state 0” or “state 1” depending on a former state. Further, when a phase of the frequency-divided reference signal FREF′ is more delayed than that of the frequency-divided feedback signal FVCO′, the state value moves to “state 0” or “state 2” depending on a former state. Moreover, when the frequency-divided reference signal FREF′ and the frequency-divided feedback signal FVCO′ are locked, “state 0” is maintained.
However, as illustrated in FIG. 2C, delayed time of each logic circuit device of the phase frequency detector may periodically cause an abnormal interval (Trst interval) in which both the up signal UP and the down signal DN become 1. Also, despite the unlock state, the lock detection circuit may detect a lock state.
Therefore, research into a lock detection circuit capable of taking the delayed time of a logic circuit device to accurately detect a lock state has been progressively carried out, and as a result, a lock detection circuit as illustrated in FIG. 3 has been disclosed.
FIG. 3 schematically illustrates a conventional lock detection circuit.
Referring to FIG. 3, the conventional lock detection circuit includes a delay circuit, seven NAND gates, two T-flip-flops, and four inverters, and only when a time difference between an up signal UP and a down signal DN is smaller than a predetermined reference signal FREF, a high lock detection signal LKD is output.
However, in order to implement the lock detection circuit, many logic circuit devices should be connected to each other, resulting in the complicated hardware implementation, its large size, and increased power consumption.